5GHz CMOS Resonant Clock Buffer with Quadrature Generation for Fiber Optic Applications

Clock buffers constitute a major source of power dissipation in VLSI circuits. In CMOS the load is primarily capacitive and hence an inductive shunt can reduce real power needs. This almost-adiabatic topology is referred to as a resonant buffer. Two resonant buffers can be actively controlled by additional variable capacitance, to deliver quadrature signals from a single incoming clock. The cost of this quadrature generation is added complexity of control algorithm and the advantage is 85% less power than alternate methods. This topology is used to create quadrature signals and drive the clock inputs of a bang-bang half-rate phase detector in a 10GBit/sec Clock and Data Recovery Circuit. The 0.13um CMOS implementation shows significant power savings. A useful closed form expression for jitter transfer characteristic of generic linear-time-invariant filters is derived and applied to the proposed buffer to show it can be transparently integrated in existing CDR architectures. The work for this thesis was conducted in part at Analog Devices Inc. . VI-A Company Thesis Supervisor: Lawrence De Vito Title: Fellow, Analog Devices Inc. Thesis Supervisor: Anantha P. Chandrakasan Title: Professor, Microsystem Technology Laboratories